Siemens Aprisa

Design your photonic integrated circuit in a layout-centric flow. The designer can implement their design using either a drag-and-drop or a script-driven methodology. Both of those are in the same full custom IC design layout editor that drives the physical verification and tape-out processes. L-Edit Photonics enables the fast creation of a photonic design using a drag-and-drop methodology in an IC layout editor, without having to write a single line of code. Once the design is completed, a netlist can be extracted for photonic simulation. PIC design in a complete IC layout editor, Create a layout without writing a line of code. Supports a layout-centric design flow where a schematic is not needed. Schematic flow optional with S-Edit. A simulation netlist can be created as input into a photonic simulator. Photonic simulation is supported through integration with our partners. Photonic PDKs are available from multiple foundries.

PowerPro offers the most comprehensive set of features to RTL designers to “design-for-low-power”. It offers power estimation for both RTL and Gate-level designs, early power checks to quickly find power issues during RTL development, and clock and memory gating to optimize the design for power. PowerPro offers the most comprehensive set of features to RTL designers to “design-for-low-power”. It offers power analysis for both RTL and gate-level designs, early power checks to quickly find power issues during RTL development, and clock and memory gating to optimize the design for power. PowerPro delivers highly accurate estimations that are within 10% of signoff. This technology is built on advanced engines that enable a broad spectrum of analysis capabilities. PowerPro’s automatic power optimization delivers low-power RTL automatically with integrated logic equivalence checking. PowerPro’s automatic optimization is the only proven low-power RTL generation technology in the market today.