Search Results for "simulator processor"
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Showing 46 open source projects for "simulator processor"
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PicoBlaze_Simulator_in_JS
A simulator of Xilinx PicoBlaze soft-processor, runnable in browsers.
A web-based assembler for and emulator of Xilinx PicoBlaze. -
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Parallel and Distributed Process System
NOTICE OF CONSOLIDATION & PARTNERSHIP PENDING As of April 2026, the 20
NOTICE OF CONSOLIDATION & PARTNERSHIP PENDING As of April 2026, the 20 pipelines of the QCAUS/PDPBioGen suites are undergoing consolidation for high-scale institutional research. Core 'Ford 2026' algorithms remain the proprietary IP of the Ford Peace and Justice Foundation. Academic users at partner institutions are currently performing validation; all other commercial inquiries must contact the author Computational Neuroscience: Large-scale neural population dynamics, brain-inspired... -
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simdop
Application for simulation of microprogrammed processor DOP
...With this simulator you can simulate one clock or large amount of microinstructions of DOP processor. It's easy and user-friendly. -
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Uruk GNU/Linux
Uruk GNU/Linux fast, simple and strength GNU/Linux distribution
Uruk GNU/Linux is a distribution of the GNU operating system, with the Linux-libre kernel. It comes ready for home and office use, and programs are easy to find and install. In this time Uruk GNU/Linux is based on PureOs core. Uruk GNU/Linux use "Mate DE" as a default desktop -
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FastSim consists of: - 'Facile' a highly flexible and expressive processor-architecture specification-language. - A compiler for the specifications which produces high-performance, fast-forwarding simulators.
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wrenss
Water Resources Evaluation of Non-point Silvicultural Sources (WRENSS)
The wrenss project is a water yield post-processor for the Forest Vegetation Simulator (FVS, see open-fvs and open-suppose) model. FVS provides the vegetative input and the user provides monthly precipitation and parameters for water yield calculations. Wrenss calculates changes in annual water yield resulting from forest management or disturbance. The model has been fit to the contiguous United States. -
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Saksham: Multi-Core Processor Simulator
x86 Multi-Core Microprocessor and assembler simulator written in C++
Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator. A C++ Project aimed at creating a platform for simulating basic features (Register and Instruction Set) of a x86 Based Multi Core Microprocessor and assembler family. This project is implementation of the concept presented in the paper: https://ieeexplore.ieee.org/document/5231896 Documentation: https://sourceforge.net/p/saksham/wiki/Home/ -
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simutron
AVR simulator IDE
Electronic circuit simulator. Simple environment to run and debug firmware for AVR 8-bit microprocessors. Able to run arduino firmware. Internally this program uses the open source Simavr AVR Processor Simulator (https://github.com/buserror/simavr) and wraps all its functions in a GUI shell. Setups for firmware debugging scenarios can be created dynamically. -
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PPface
PPface is vector processor emulator / simulator
PPface is vector processor emulator / simulator (SIMD array processor with 1-bit processing elements). VEPRAN language used to design parallel algorithms and operate data slices. The system allows to visualize algorithm work by viewing vector memory and registers, it supports debugging and animated program execution. To run this app on 64-bit system please install Windows Virtual PC and Windows XP Mode. -
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dps8m
A simulator for the Multics dps-8/m mainframe
...2015-11-05: The Ritter Park RCC Multics installation was "[T]aken down after a month of uptime." 2017-03-07: The DPS8M Development Team released Multics Release MR12.6f. 2017-07-08: Announcing v1.0 The purpose of this project is to create a simulator reproducing in sufficient detail the function and capabilities of the Honeywell/Bull dps-8/m processor with the ultimate goal of resurrecting Multi -
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or1ksim64 patch
Patch to openRISC simulator to enable 64-bit operation
This is a patch to the or1ksim simulator code in the openRISC project at opencores.org to provide 64-bit support. The current or1ksim simulator code "only" emulates a 32-bit processor and 64-bit operation is envisaged by the openRISC specification document, so this patch sets out to provide it by changing the simulated architecture to contain 64-bit registers and addresses. -
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or1ksim64KPU
Krypto-processor (KPU) on OpenRISC architecture
This simulation of a KPU (general purpose Krypto-processor) extends the OpenRISC or1ksim simulator to cover the OR 64-bit standard, and runs encrypted in user mode with 32-bit data and addressing encrypted in 64 bits of physical space. Privileged supervisor processes cannot read user-mode data, nor modify it without being noticed. This demonstration shows that it is possible to modify standard architectures (such as OR) to support KPU operation. -
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SimuS
A didatic processor simulator
This is an integrated IDE, consisting of an editor, an assembler and a simulator for an 8-bit didatic processor named Sapiens. It is intended for educational purposes. It is written in Object Pascal, and fully compatible with Lazarus framework. You can find the sources for the version compatible with Raspberry Pi at https://github.com/sottam/simus. Check our new book: https://goo.gl/cSH6rU -
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QNICE is a simple 16 bit processor intended to teach the basics of hardware design as well as operating system design. A TTL implementation is planned, a FPGA implementation is available here: http://qnice-fpga.com. Currently there exists a C based simulator and an assembler.
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RCLcalculators
RCL, a simulator for Texas Instrument calculators from the 70's.
Calculators became available in the early 70's, soon after the integrates circuits, and several companies were competing with each other for a share of this market. Texas Instruments was one of the bigger companies producing calculators. With RCL it is possible to recreate the TI calculators, strating with the Ti59e, with 960 program steps and a persistant memory (a combination of the the Ti58C and the Ti59). RCL offers any person interested in the ancient ones in calculators (more... -
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DigMIPS
A simple MIPS processor for Chipmunk DigLog circuit simulator
- DigMIPS is a simple 1-cycle-per-instruction MIPS processor working under DigLog circuit simulator. - DigMIPS is provided with an assembler and a C compiler. - DigMIPS serve as a nice support to teach the basics of computer architecture. Features: - 8 instructions - 8K RAM + 8K ROM - I/O periphals (keyboard and teletype screen) Software: - DigASM (assembler) - DigCC (C compiler) -
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SkyEye
a very fast full system simulator
SkyEye is a very fast full system simulator which takes llvm as IR of dynmic compiled framework.. It can simulate series ARM, Coldfire,Mips, Powerpc, Sparc, x86, TI DSP and Blackfin DSP Processor. Also can simulate multicore system by the multicore of host. The commercial support is provided by DigiProto Co. (http://www.digiproto.com) -
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openDLX
A DLX/MIPS processor simulator
openDLX is a DLX/MIPS ISA compatible pipeline simulator. (Visit https://github.com/smetzlaff/openDLX for the latest development version or if You want to contribute.) -
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ParallelSim
ParallelSim is a parallel processor simulator written in java.
ParallelSim is a parallel processor simulator written in Java which shows the effect of increasing the workload keeping the number of processing elements constant in one simulation. The number of processors is scalable and can be increased in subsequent iterations of simulation. The parameters like initial load, load offset, number of processors are declared as constants and can be changed directly in the source code to emulate different scenarios. -
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SCHEDuler SIMULAtor (originally sched_sim) is a simple C++ event driven simulator of scheduling policies (single processor). Currently supported scheduling policies are: FIFO, LIFO, EDF, LST, RM, DM.
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DASiT
DASiT (DLX-Altivec Simulator Tool)
DASiT is a simulation teaching tool based on DLX processor that includes multimedia set-instructions by incorporating AltiVec SIMD extensions. The tool developed in Java displays DLX pipeline execution with its data path that incorporates visualization of memory and register. It is considered as a complement in undergraduate computer design and computer architecture subjects. -
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Based on IVM(Illinois Verilog Module), redeign an Synthesizable verilog simulator for processor simulation
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Processor and realtime viewer for the program VXFlow (http://www.morgenthal.org/vxflow/), an numerical flow field simulator, written by Prof. Dr. Guido Morgenthal (http://www.uni-weimar.de/Bauing/MSK/?lang=en). This project uses the gloost framework.
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An Education Microprocessor Simulator, based off the a design by Charles Stroud (http://www.eng.auburn.edu/~strouce/ausim.html), this will extend the capabilities and UI of the original and will have a VHDL implementation for educational purposes.
