Search Results for "wifislax-4-11-1-final"
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Showing 63 open source projects for "wifislax-4-11-1-final"
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GHDL
VHDL 2008/93/87 simulator
...Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a code generator (LLVM, GCC or, x86_64/i386 only, a built-in one), it is much faster than any interpreted simulator. It can handle very large designs, such as leon3/grlib. GHDL runs on GNU/Linux, Windows and macOS; on x86, x86_64, armv6/armv7/aarch32, aarch64 and ppc64. You can freely download nightly assets, use OCI images (aka Docker/Podman containers), or try building it on your own machine. -
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pyrpl
PyRPL turns your Red Pitaya into a powerful analog feedback device.
...PyRPL implements various digital signal processing (DSP) modules (see features below). It allows to arbitrarily interconnect the available DSP modules and retrieve signal values on timescales below 1 ms. The graphical user interface (GUI) provides a realtime display of the various measurement instruments and allows the easy configuration of DSP signal chains and feedback controllers. At the highest abstraction level, arbitrary feedback sequences can be defined to fulfill tasks as complex as approaching and locking a resonance of a high-finesse Fabry-Perot cavity (tested up to finesse=100,000). -
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VlibTools
Tools and libraries for use with systemc and verilog
Tool suite and libraries for developing system-c models. Tools for managing RTL projects. -
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and... -
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COFILOS
A Development Framework for Coldfire
Contains a framework for Coldfire MCUs like 52254. The framework supports a Command Line Interface (CLI) that may work from Serial port, USB or ENET. The framework uses Processor Expert and IDE requirement is MCU Eclipse 10.4 from Freescale. Includes the FunkOS Realtime Operating System by Funkenstein Software Consulting, available at http://funkos.sourceforge.net Mainly it is a support package for the development board Perseus, but I have ported also the RTOS to MCF52233DEMO... -
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cMIPS
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips The code here is no longer up to date. The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%... -
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libVerilogVPI
SEL for access verilog via PLI/VPI API. Tested with Icarus Verilog.
SFENCE Extension Library (SEL) for access verilog function via PLI/VPI API to calls of standard SFENCE Function_Function objects. -
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A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.
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FPGA starterkit essentials
basic debug tools while using FPGA boards
Module 1: durchblicker: embedded Logicanalyzer with direct output on VGA-monitor -
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openAut
Open Source Hardware For Industrial Automation
This project is aimed at producing open source hardware for real time use in industrial automation. This project will have a few sub-projects that will focus on individual hardware for various industrial purpose. Some of the sub-projects will be of type Field-IO Modules development, Analog-IO Module development etc. -
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Anie
PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e
Embedded system design (VHDL description) based on Xilinx's Spartan3E Development Kit to perform real-time PID control and monitoring of time critical plants such as brushless DC motors, maglevs... vimeo.com/channels/anie prezi.com/gpbycavq499c/anie/ -
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Sharp MZ800 univerzalni karta periferii 1 ----------------------------------------- Contains peripherals: emulator of FDC WD279x, RTC, single channel SIO, repository manager, LAN10Mbit Chips on the card: STM32F101, XC9356, ENC28J60, FT232RL, MAX3232
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Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation) -
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FAZIA DAQ
The aim of FAZIA project is to build a 4Pi array for charged particles
The FAZIA project groups together more than 10 institutions in Nuclear Physics, which are working in the domain of heavy-ion induced reactions around and below the Fermi energy (10-100AMeV). The aim of the project is to build a 4Pi array for charged particles, with high granularity and good energy resolution, with A and Z identification capability over the widest possible range. It will use the up-to-date techniques concerning detection, signal processing and data flow, with full digital... -
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smPla
SystemVerilog module to substitute Verilog PLA system tasks.
SystemVerilog module that models the following PLA system tasks of Verilog: $a/sync$and$array $a/sync$nand$array $a/sync$or$array $a/sync$nor$array $a/sync$and$plane $a/sync$nand$plane $a/sync$or$plane $a/sync$nor$plane. -
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Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )
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Este proyecto presenta GraphUIS, una implementación de un periférico de video en un FPGA como un diseño modular caracterizado por no tener memoria dedicada. Se desarrolló como un proyecto académico en la Universidad Industrial de Santander.
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Devellopement d'un controlleur d'affichage (VIC) du commodore 64 embarqué dans un FPGA avec controlleur d'animation integré.
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xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.
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A free VHDL IPs for general purpose FPGA developpement. Need GRLIB to work properly, to setup see README.
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This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee.
