Search Results for "net-snmp-5.9.4-1.x64.exe"

...Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a code generator (LLVM, GCC or, x86_64/i386 only, a built-in one), it is much faster than any interpreted simulator. It can handle very large designs, such as leon3/grlib. GHDL runs on GNU/Linux, Windows and macOS; on x86, x86_64, armv6/armv7/aarch32, aarch64 and ppc64. You can freely download nightly assets, use OCI images (aka Docker/Podman containers), or try building it on your own machine.

Platform for advanced open source IP-Core development, i. e. dynamic memory controllers for FPGAs.

...PyRPL implements various digital signal processing (DSP) modules (see features below). It allows to arbitrarily interconnect the available DSP modules and retrieve signal values on timescales below 1 ms. The graphical user interface (GUI) provides a realtime display of the various measurement instruments and allows the easy configuration of DSP signal chains and feedback controllers. At the highest abstraction level, arbitrary feedback sequences can be defined to fulfill tasks as complex as approaching and locking a resonance of a high-finesse Fabry-Perot cavity (tested up to finesse=100,000).

Contains a framework for Coldfire MCUs like 52254. The framework supports a Command Line Interface (CLI) that may work from Serial port, USB or ENET. The framework uses Processor Expert and IDE requirement is MCU Eclipse 10.4 from Freescale. Includes the FunkOS Realtime Operating System by Funkenstein Software Consulting, available at http://funkos.sourceforge.net Mainly it is a support package for the development board Perseus, but I have ported also the RTOS to MCF52233DEMO...

ASIC research and development

Module 1: durchblicker: embedded Logicanalyzer with direct output on VGA-monitor

This project is aimed at producing open source hardware for real time use in industrial automation. This project will have a few sub-projects that will focus on individual hardware for various industrial purpose. Some of the sub-projects will be of type Field-IO Modules development, Analog-IO Module development etc.

Sharp MZ800 univerzalni karta periferii 1 ----------------------------------------- Contains peripherals: emulator of FDC WD279x, RTC, single channel SIO, repository manager, LAN10Mbit Chips on the card: STM32F101, XC9356, ENC28J60, FT232RL, MAX3232

This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)

Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )

Este proyecto presenta GraphUIS, una implementación de un periférico de video en un FPGA como un diseño modular caracterizado por no tener memoria dedicada. Se desarrolló como un proyecto académico en la Universidad Industrial de Santander.

Devellopement d'un controlleur d'affichage (VIC) du commodore 64 embarqué dans un FPGA avec controlleur d'animation integré.

This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee.

This project aims at creating an open-source SoC that will support the Google TV platform.

A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.

The project uses the infrared camera from the wiimote to track hand gestures. This tracking is performed on an Altera DE2-70 FPGA

Attempt to implement DEC PDP-11 minicomputer in Xilinx FPGA

FPGAmer is a framework to develop embedded games. Our development platform is the Xilinx University Program Virtex-II-Pro but not limited to that. FPGAmer includes custom hardware components plus a custom software framework and some sample games.

Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.

The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research

CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for Win32, bus easily portable for other platforms

Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai

This is the award-winning FALCON I object recognition system! Capable of tracking up to 12 different objects simultaneously, and with over 6 times the raw resolution of the CMUCam, this is one of the most powerful vision systems in its class.

This project aims to generate video signal using an FPGA development board

the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol