Showing 2 open source projects for "virtual memory"

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  • The full-stack observability platform that protects your dataLayer, tags and conversion data Icon
    The full-stack observability platform that protects your dataLayer, tags and conversion data

    Stop losing revenue to bad data today. and protect your marketing data with Code-Cube.io.

    Code-Cube.io detects issues instantly, alerts you in real time and helps you resolve them fast. No manual QA. No unreliable data. Just data you can trust and act on.
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  • SoftCo: Enterprise Invoice and P2P Automation Software Icon
    SoftCo: Enterprise Invoice and P2P Automation Software

    For companies that process over 20,000 invoices per year

    SoftCo Accounts Payable Automation processes all PO and non-PO supplier invoices electronically from capture and matching through to invoice approval and query management. SoftCoAP delivers unparalleled touchless automation by embedding AI across matching, coding, routing, and exception handling to minimize the number of supplier invoices requiring manual intervention. The result is 89% processing savings, supported by a context-aware AI Assistant that helps users understand exceptions, answer questions, and take the right action faster.
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  • 1
    SnappyData

    SnappyData

    Memory optimized analytics database, based on Apache Spark

    SnappyData (aka TIBCO ComputeDB) is a distributed, in-memory optimized analytics database. SnappyData delivers high throughput, low latency, and high concurrency for a unified analytics workload. By fusing an in-memory hybrid database inside Apache Spark, it provides analytic query processing, mutability/transactions, access to virtually all big data sources and stream processing all in one unified cluster. One common use case for SnappyData is to provide analytics at interactive speeds over...
    Downloads: 5 This Week
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  • 2
    RISC-V BOOM

    RISC-V BOOM

    SonicBOOM: The Berkeley Out-of-Order Machine

    The riscv-boom project (also called BOOM or SonicBOOM) implements a high-performance, synthesizable out-of-order RISC-V core written in the Chisel hardware construction language. It targets the RV64GC (i.e. 64-bit with general + compressed + floating point) instruction set and supports features such as virtual memory, caches, atomics, and IEEE-754 floating point. The design is parameterizable, meaning users can tune pipeline widths, buffer sizes, functional units, and other microarchitectural knobs to explore tradeoffs. It is capable of booting Linux and running standard benchmarks, and its performance (measured in CoreMarks/MHz) is competitive with commercial cores. ...
    Downloads: 0 This Week
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